1. Field of the Invention
The present invention relates to a polishing liquid, which is used in a process for the production of semiconductor integrated circuits, and a polishing method using the same. More specifically, the present invention relates to a polishing liquid, which can be preferably used for the gate formation of a semiconductor substrate, and a polishing method using the same. In particular, the present invention relates to a polishing liquid for polishing a semiconductor substrate having a layer containing polysilicon or a modified polysilicon by chemical mechanical polishing and a polishing method using the same.
2. Description of the Related Art
In recent years, in the development of semiconductor devices represented by a semiconductor integrated circuit (hereinafter, referred to as an “LSI” in some cases), high density and high integration through refining and lamination of wirings have been required in order to realize size reduction and high speed. As a technique for achieving the purpose, various techniques such as chemical mechanical polishing (hereinafter, referred to as “CMP” in some cases) have been used. The CMP is an essential technique in the case of carrying out surface planarization of a film to be processed such as an interlayer insulating film, formation of plugs, formation of embedded metal wirings, or the like, and is used for smoothening of a substrate or the like.
A general method of CMP is a method in which a polishing pad is adhered on a circular polishing platen (platen), the surface of the polishing pad is dipped in a polishing liquid, a surface (surface to be polished) of a substrate (e.g., wafer) is pressed against the pad, and both the polishing platen and the substrate are rotated in a state of being applied with a predetermined pressure (polishing pressure) from the rear face of the pad, to planarize the surface of the substrate by the mechanical friction generated.
Recently, CMP has been applied to the respective processes in the production of semiconductors, and in one embodiment thereof, for example, CMP is applied to a process for gate formation in the fabrication of transistors.
Herein, in conventional transistors, a gate mainly including a modified polysilicon obtained by introducing impurities such as B (boron) into polysilicon has been prepared. However, in transistors after 45 nm generations, the use of a gate insulating film having a high dielectric constant (a High-k film) and a metal gate electrode in place of the conventional polysilicon has been examined, in order to achieve both reduction in electric power consumption and high current driving ability. Some techniques to which these have been applied have been proposed. For example, a method has been proposed, in which a dummy insulating film and a dummy gate electrode are formed, a source-drain diffusion layer is formed by introducing impurities to a polycrystalline silicon film in a self-aligning manner, then the dummy insulating film and the dummy gate electrode are removed, and then a gate insulating layer having a high dielectric constant and a metal gate electrode are formed (see, for example, Japanese Patent Application Laid-Open (JP-A) Nos. 2006-339597, 2006-344836, and 2007-12922).
Further, some techniques concerning the method for forming a metal gate electrode have been proposed. As one example thereof for practical use, there is a fully silicided gate (hereinafter, may be referred to as a “FUSI gate”). The FUSI gate is formed by siliciding a gate electrode formed using polysilicon in a manner substantially similar to that in the conventional CMOS (Complementary Metal Oxide Semiconductor) process. Conventionally, only the upper portion of a gate electrode is silicided; however, in the FUSI gate, the entire gate electrode is silicided. As compared with the technique of forming a metal gate electrode by a Damascene process, FUSI is greatly advantageous in terms of process construction, since the knowhow of the conventional CMOS process is applicable.
In recent years, a method of selectively performing CMP with respect to the polysilicon or the like, and a second and/or third material at the periphery thereof, in the formation of a gate using such polysilicon or modified polysilicon (hereinafter, may be merely referred to as “polysilicon or the like”) has been proposed (see, for example, JP-A No. 2005-93816). However, when a body to be polished which contains polysilicon or the like is polished by CMP using a conventionally known polishing liquid, there is a problem in that polysilicon or the like which is intended to remain as a gate material may be excessively polished. This problem may lead to cause other problems such as deterioration in performance of LSI to be obtained or the like.